1. Field of the Invention
The present invention is directed to an apparatus for providing pulse delay compensation in a phase lock loop for use in a frequency synthesizer. Specifically, the pulse delay compensation of the present invention compensates for spurious frequencies which would develop from variations in pulse period in the phase lock loop and which in turn results in jittering and poor spectral purity for the output frequency signals from the frequency synthesizer.
2. Description of the Prior Art
Frequency synthesizers have been used to provide for the generation of output signals of a desired frequency. In particular, one type of frequency synthesizer uses a phase lock loop to control the frequency of the output signal. In this type of frequency synthesizer, a frequency reference signal is applied as a first input to a phase detector and with the output of the phase detector coupled through a low pass filter to be applied as an input to a voltage controlled oscillator. The output of the voltage controlled oscillator is the desired output signal of the desired frequency and in order to control the frequency of the output signal, a feedback path is established between the output of the voltage controlled oscillator and a second control input for the phase detector. The feedback path includes a frequency counter to divide the frequency of the output signal from the voltage controlled oscillator to control the phase detector in accordance with a coincidence between both inputs to the phase detector.
This type of conventional single phase lock loop frequency synthesizer has a practical limitation as to the number of digit resolution that can be achieved. For example, in some cases as low as three (3) digits may be considered to be not practical because the output signal may be degraded due to a spurious frequency level. In order to increase the number of digit resolution the prior art has used a phase accumulator circuit forming part of the feedback in the phase lock loop. The phase accumulator technique, in theory, has almost no practical limit as to the number of digit resolution. However, this phase accumulator technique will also produce a high level of spurious frequencies since there is a variation in the pulse period in the feedback signal which results from the use of the phase accumulator circuit.
In the prior art the counter in the feedback path is modified and programmed to divide either by N (a positive integer) or divide by N+1 at periodic times during a sequence. The counter could also divide by N-1 instead of N+1 but in the present application, the example used is to divide by N+1. By periodically dividing by N+1 the practical effect is to increase the number of digit resolution in an almost unlimited fashion. However, because the output signal from the voltage controlled oscillator is sometimes divided by N and other times by N+1, the pulse period for the divisions is not always equal. The variation in the pulse period therefore results as jittering and poor spectral purity in the output signal from the voltage controlled oscillator.